In the field of electronics it has been a continual goal of engineers to reduce the size of systems. The majority of system size reduction has been achieved through utilization of integrated circuit technology. A primary aim of these technologies has been to reduce transistor size and integrate increasingly dense circuitry and functionality within a single integrated circuit.
In order to connect integrated circuits to operational electronic systems, some means must be available for transferring signals and power into and out of the integrated circuit. Typically, each chip is placed into its own chip package. Wires are then connected between bond pads on the chip and pins on the package. Several such packages (DIPs, SIPs, LCC, PGA, etc.) are then assembled onto various media (ceramic, epoxy, metallized layers, etc.) to perform useful functions. For purposes of this description define "chip" to mean a completed integrated circuit die prior to the formation of any physical or electrical connection thereto. The "major surface" of the chip is defined to be that surface on which the integrated electronics have been disposed. The "back surface" of the chip shall be that surface opposite the major surface.
Packaging technology has essentially allowed for the placement of a chip into a protective environment which allows for the interconnection of the chip to external circuitry. The integrated circuit is then electrically connected (bonded) to external connectors. Historically integrated circuit packages have been cylindrical cans with wire pins housing small chips. Subsequently Dual-In-Line packages (DIPs) made of plastic or ceramic with two parallel rows of pins became the industry standard. Due to increased lead count (pin) requirements Pin Grid Array (PGA) packages, which have a matrix of pins extending from the bottom of the package, and Leadless Chip Carrier (LCC) packages, which have an array of external connector lands around the package edge, have been developed.
Typical integrated circuit packages contain only one integrated circuit. The package "footprint" is many times the area of the integrated circuit. To satisfy the requirements for increasing the density of electronic circuitry within a system, attempts have been made to employ three-dimensional stacking of integrated circuits. Such three-dimensional techniques attempt to overcome the difficulties which face the designer of hybrid circuits. A hybrid circuit typically consists of a two dimensional structure made up of a large insulated substrate, usually ceramic, onto which are connected in lateral orientation, two or more chips, packaged chips and/or other electronic components. These techniques are well known in the art, but their effectiveness at significantly increasing circuit density is somewhat limited.
A technique proposed in Carson, et al., U.S. Pat. No. 4,551,629 involves the three dimensional stacking of chips. While this stack of chips has a higher packaging density than any of the previously described techniques there are severe manufacturing, thermal and testing difficulties which make this technique difficult and expensive to implement. These difficulties relate to the complexity of the stacking process together with the processing problems associated with attempting to form external connections to the semiconductor stack. The package cannot easily be made hermetic. Special chips must be designed and configured for use with this technique. Further, complex wafer processing techniques must be applied to the edges of the stack prior to external connection. Because of this additional processing the circuits cannot be tested at each step of the processing causing extensive manufacturing yield loss. A severe limitation is imposed by the requirement that all of the stacked devices must have the equal dimensions.
It is an object of this invention to provide a high density packaging technology for chips.
It is another object of this invention to use this packaging technology to provide a variety of high density packages for chips useful for a variety of applications.
It is another object of this invention to have the manufacturing steps for forming high density packages use industry standard packaging techniques.
Still another object of this invention is to provide high density integrated circuit packages which are suitable for use with standard commercial chips of various dimensions.
Yet another object of this invention is to provide efficient and convenient means for cooling such high density chip packages.
A further object of this invention is to provide an efficient means for the interconnection of the chips in such a high density package.
An additional object of this invention is to provide a structure which is easy to test both during and subsequent to manufacturing.